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Delta-Sigma ADC

Simulation of a first-order delta-sigma analog-to-digital converter.

You can also find this example as a single file in the GitHub repository.

Delta-Sigma ADC Principle

A delta-sigma ADC works by:

Oversampling the input signal at a high frequency
Using a 1-bit quantizer (comparator)
Negative feedback through a DAC to shape quantization noise
Digital filtering (FIR) to downsample and reconstruct the signal

The key advantage is that quantization noise is pushed to high frequencies (noise shaping), where it can be filtered out.

The system uses DAC, Comparator, SampleHold, and FIR blocks to implement a complete delta-sigma ADC with digital filtering.

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System Parameters

We set the key parameters:

Clock frequency: 100 Hz (oversampling rate)
Reference voltage: 1.0 V
FIR filter: 20 taps, cutoff at Fs/50

The input signal is a 1 Hz sine wave, so the oversampling ratio is 100.

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Block Diagram

We create the blocks for the delta-sigma modulator:

src: Input signal (sine wave)
sub: Subtractor (input - feedback)
itg: Integrator (loop filter)
sah: Sample & Hold
qtz: Comparator (1-bit quantizer)
dac: 1-bit DAC for feedback
lpf: FIR lowpass filter for reconstruction

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Connections

The connections form the delta-sigma loop with digital filtering.

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Simulation

We use an adaptive solver (RKBS32) with a maximum timestep to handle the discrete-time sampling events properly.

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12:43:34 - INFO - LOGGING (log: True)
12:43:34 - INFO - BLOCKS (total: 9, dynamic: 1, static: 8, eventful: 4)
12:43:34 - INFO - GRAPH (nodes: 9, edges: 13, alg. depth: 2, loop depth: 0, runtime: 0.083ms)
12:43:34 - INFO - STARTING -> TRANSIENT (Duration: 2.00s)
12:43:34 - INFO - --------------------   1% | 0.0s<0.8s | 2470.4 it/s
12:43:34 - INFO - ####----------------  20% | 0.2s<0.5s | 3059.3 it/s
12:43:34 - INFO - ########------------  40% | 0.4s<0.4s | 2911.9 it/s
12:43:34 - INFO - ############--------  60% | 0.5s<0.3s | 3091.8 it/s
12:43:34 - INFO - ################----  80% | 0.7s<0.2s | 2663.2 it/s
12:43:35 - INFO - #################### 100% | 0.9s<--:-- | 3105.1 it/s
12:43:35 - INFO - FINISHED -> TRANSIENT (total steps: 2402, successful: 2401, runtime: 893.57 ms)

Results

The plots show:

src (blue): Original analog input signal
qtz (orange): 1-bit quantizer output (high-frequency switching)
dac (green): 1-bit DAC feedback signal
lpf (red): Reconstructed signal after FIR filtering

Notice how the 1-bit stream encodes the analog signal, and the FIR filter successfully reconstructs it.

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